1. Technical Field
The present invention relates to a semiconductor device and to a method of manufacturing the semiconductor device.
2. Background Art
In order to increase a degree of integration and to simplify a manufacturing process in a BiCMOS semiconductor integrated circuit and the like, it has been conventional to employ a method for forming an electrode through direct contact between refractory materials, such as between silicon and poly-silicon or between poly-silicon and poly-silicon.
FIGS. 5, 6 and 7 are drawings to explain an example of BiCMOS semiconductor device according to a prior art that includes a direct contact portion between the refractory materials and a method of manufacturing thereof. In the drawings, reference numeral 1 is a p-type silicon substrate; numeral 2 is an n-type buried and diffused layer; numeral 3 is an n-type epitaxial layer; numeral 4 is a p-type isolation layer; numeral 5 is a p-type well layer. Numeral 6 is a LOCOS (local oxidation of silicon) oxide film; numeral 7 is a gate insulating oxide film; numeral 8 is a p-type base layer; numeral 9 is an n-type emitter layer; and numeral 10 is a lower layer poly-silicon electrode film. Numeral 11 is an upper layer poly-silicon electrode film; numeral 12 is a WSi electrode film; numeral 13 is a p-type source/drain diffused layer; and numeral 14 is an n-type source/drain diffused layer. Numeral 15 is an interlayer insulating film comprising BPSG (Boro-phospho Silicate Glass) or the like; numeral 16 is a metallic electrode film composed of an AlSiCu film or the like. Numeral 17 is a final passivation film composed of a p-SiN film or the like; and numeral 30 is a natural oxidation film.
Now, a method of manufacturing the BiCMOS semiconductor device in the prior art will be described with reference to FIGS. 6(a)-6(c) and 7(a)-7(c).
First, as shown in FIG. 6(a), the n-type epitaxial layer 3 is formed on the entire surface of the p-type silicon substrate 1 after selectively forming the n-type buried duffused layer 2 in the substrate. Then, the LOCOS oxide film 6 is formed by LOCOS process after forming the p-type isolation layer 4 and the p-type well layer 5. Further, the gate insulating oxide film 7 of about 10 nm to 100 nm in thickness is formed.
Then, as shown in FIG. 6(b), the lower layer poly-silicon electrode film 10 is formed on the entire surface of the substrate by low pressure CVD after selectively forming the p-type base layer 8 by photolithography and ion implantation. Then, the lower layer poly-silicon electrode film 10 and the gate insulating oxide film 7 are selectively etched using a resist formed by photolithography, and arsenic is implanted by ion implantation, whereby the n-type emitter layer 9 is formed.
Then, washing or cleaning of organic residue from the resist and so on used in the photolithography process, is carried out prior to the formation of the upper layer poly-silicon electrode film 11. A series of cleaning processes is shown in FIG. 8. In the final deionized-water rinsing step (S9) and in the drying (IPA vapor drying, spin drying or warm air drying) step (S10) in the cleaning process, it sometimes happens that a natural oxidation film 30 grows with a locally large variation in thickness. The natural oxidation film grows due to a surface oxidation reaction in the chemical processing step and/or reaction of water remaining due to insufficient drying in the drying step.
Then, as shown in FIG. 6(c), arsenic ions are implanted in the entire surface of the upper layer poly-silicon electrode film 11 after forming the upper layer poly-silicon electrode film 11 by low pressure CVD, and then, the arsenic ions implanted in the upper layer poly-silicon electrode film 11 are activated by heat treatment at about 800° C. to 900° C. and diffused into the lower layer poly-silicon electrode film 10, so that the resistance between the upper layer poly-silicon electrode film 11 and the lower layer poly-silicon electrode film 10 is reduced.
Then, as shown in FIG. 7(a), the electrode film 12 of WSi, being one of the low resistant high refractory metal compounds, is formed by sputtering. Subsequently, the WSi electrode film 12, the upper layer poly-silicon electrode film 11, and the lower layer poly-silicon electrode film 10, of which the resistance has been reduced, are selectively etched by photolithography and etching, so that a bi-polar emitter electrode and a MOS gate electrode are formed.
Then, as shown in FIG. 7(b), the p-type source/drain diffused layer 13 and the n-type source/drain diffused layer 14 are selectively formed by photolithography and ion implantation.
Then, as shown in FIG. 7(c), after forming the interlayer insulation film 15 composed of a BPSG film or the like on the entire surface of the substrate, a contact hole is formed by photolithography and etching. Then, the metallic electrode film 16 composed of an AlSiCu film or the like is formed, and finally the final passivation film 17 composed of a p-SiN film or the like is formed. The conventional semiconductor device is manufactured through the above-described process.
Since the conventional semiconductor device including the direct contact portion between the refractory materials, for example, between silicon and poly-silicon, poly-silicon and poly-silicon or the like, has been manufactured through the foregoing procedure, there arise several problems as discussed below.
In the final deionized-water rinsing step (S9) and the drying step (S10) of the cleaning process employed prior to the formation of the upper layer poly-silicon electrode film 11, a natural oxidation film 30 in the form of a stain, referred to as a water-mark, may grow with a locally wide variation in thickness on the surface of the silicon wafer, resulting from a naturally drying water drop on the surface during or after the drying step. However, as the phenomenon of water drop adhesion is a phenomenon depending upon probability, the natural oxidation film 30 is formed, in some cases, on the interface between the n-type emitter layer 9 and the upper layer poly-silicon electrode film 11 as shown in FIG. 9(a), while in some other cases, not formed as shown in FIG. 9(b). In the connection between the n-type emitter layer 9 and the upper layer poly-silicon electrode film 11, it is ideal that the natural oxidation film 30 is not formed and the contact resistance is low as shown FIG. 9(b). However, in actual practice, as shown in FIG. 9(a), the natural oxidation film 30 with large variation in local thickness is usually formed on the interface between the n-type emitter layer 9 and the upper layer poly-silicon electrode film 11, whereby variation in contact resistance occurs. Moreover, in the BiCMOS portion, as the arsenic ions implanted in the upper layer poly-silicon electrode film 11 through the natural oxidation film 30 with the wide variation of local thickness are diffused in the lower layer poly-silicon electrode film 10, the state of diffusion of the arsenic ions varies from place to place in the lower layer poly-silicon electrode film 10. As a result, a problem exists in that something abnormal takes place in device characteristics.